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Asilomar 2008

Par Emmanuel CasseauDernière modification 14/01/2009 11:12

Fast and Accurate Activity Evaluation in Multipliers, A. Tisserand, Proc. 42th Asilomar Conference on Signals, Systems and Computers (IEEE), October 2008, Pacific Grove, California, U.S.A.

Fast and Accurate Activity Evaluation in Multipliers
A. Tisserand

This article reports the first results on fast and accurate power evaluation in arithmetic operators. The proposed method uses two steps:
1) accurate useful activity evaluation, 2) fast glitching activity estimation. The first step is based on circuit emulation using FPGA. Activity counters are inserted into the low-level description of the evaluated operator. The modified description is synthesized and
downloaded into the FPGA. The operator activity behavior is emulated on the FPGA using large test vectors. The useful activity values
accumulated in the FPGA are transferred to the computer. The second step uses the formal model we proposed in [FTFC07-AT] for glitching activity estimation. The complete method is demonstrated on basic multipliers.

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